1. Field of the Invention
The present invention relates to a serial data processing circuit and, more particularly, to a serial data processing circuit for processing N serial signals during each clock cycle.
2. Description of the Related Art
A super pipeline technology is used to improve performance of LSI (Large Scale Integration) circuits. Specifically, a combinational circuit between FF (Flip-Flop) circuits is divided into a plurality of combinational circuits and one or more FF circuits are then inserted between the divided combinational circuits to serially connect the combinational circuits, thereby realizing serial data processing. This technology could increase the operating frequency of the entire combinational circuit, thereby improving the throughput performance.
Conventionally known is a pipelined RISC (Reduced Instruction Set Computer) type processor to be driven by a parallel mode (see, for example, Japanese Unexamined Patent Publication No. Hei 5-224929).
The super pipeline technology, however, has a problem of causing increase in power consumption.